Pin TDI TRSTB TMS TCK TDO STM I/ACLK I/GCLK I I/O VCC GND Function Test Data In for JTAG Active low Reset for JTAG Test Mode Select for JTAG Test Clock for JTAG Test data out for JTAG Special Test Mode High-drive input and/or array network driver High-drive input and/or global network driver High-d
3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility Rev.
C pASIC 2 HIGHLIGHTS ® QL2009 Ultimate Verilog/VHDL Silicon Solution -Abundant, high-speed interconnect eliminates manual routing -Flexible logic cell provides high efficiency and performance -Design tools produce fast, efficient Verilog/VHDL synthesis Speed, Density, Low Cost and Flexibility in One Device … 9,000 usable ASIC gates, 225 I/O pins -16-bit counter speeds exceeding 200 MHz -9,000 usable ASIC gates
QL2009-0PF144C Features
* -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 672 Logic Cells 3-35 QL2009 PRODUCT SUMMARY The Q
Datasheet Details
QL2009-0PF144C, QL2
ETC
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3.3v and 5.0v pasic 2 fpga combining speed/ density/ low cost and flexibility.
This datasheet PDF includes multiple part numbers: QL2009-0PF144C, QL2.
Please refer to the document for exact specifications by model.
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