EDE5104GBSA
Description
The EDE5104GB is a 512M bits DDR-II SDRAM organized as 33,554,432 words × 4 bits × 4 banks. The EDE5108GB is a 512M bits DDR-II SDRAM organized as 16,777,216 words × 8 bits × 4 banks. It packaged in 64-ball µBGA package. The EDE5116GB is a 512M bits DDR-II SDRAM organized as 8,388,608 words × 16 bits × 4 banks. It is packaged in 84-ball µBGA package.
Features
- 1.8V power supply
- Double-data-rate architecture: two data transfers per clock cycle
- Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data at the receiver
- DQS is edge aligned with data for READs: centeraligned with data for WRITEs
- Differential clock inputs (CK and /CK)
- DLL aligns DQ and DQS transitions with CK transitions
- mands entered on each positive CK edge: data and data mask referenced to both edges of DQS
- Four internal banks for concurrent operation
- Data mask (DM) for write data
- Burst lengths: 4, 8
- /CAS Latency (CL): 3, 4, 5...
