EMD28164PA Datasheet (Emerging Memory & Logic Solutions)

EMD28164PA, 8M x 16 Mobile DDR SDRAM

This EMD28164PA is 134,217,728 bits synchronous double data rate Dynamic RAM.

Each 33,554,432 bits bank is organized as 4,096 rows by 512 columns by 16 bits, fabricated with EMLSI’s high performance CMOS technology.

This device uses a double data rate architecture to achieve highspeed operation.

The

EMD28164PA 128M: 8M x 16 Mobile DDR SDRAM Document Title 128M: 8M x 16 Mobile DDR SDRAM Revision History Revision No.

0.0 0.1 Date Jun 4, 2007 Nov 8, 2007 History Initial Draft - Table 8 Operating AC Parameter updated for tCKE and tWR - Table 2 Bonding Pad Location and Identification Table deleted www.DataSheet4U.com - Signal names unified to /CK, /CS, /RAS, /CAS, /WE respectively (Ex.) CK#, CK, CKB unified to /CK - Corrected IDD6 value in Table 16 1.0 May 26, 2008 Release - Table 6 DC

EMD28164PA Features

* 1.8V power supply, 1.8V I/O power

* LVCMOS compatible with multiplexed address.

* Double-data-rate architecture; two data transfers per clock cycle

* Bidirectional data strobe(DQS)

* Four banks operation.

* MRS cycle with address key programs.

* CAS latency (2, 3 & 4).