* Functionality - Double-data-rate architecture ; two data transfers per CLK cycle. - Bidirectional data strobe per byte data (DQS). - No DLL ; CLK to DQS is not Synchronized. - Differential CLK inputs( CLK and /CLK ). - Commands entered on each positive CLK edge. - DQS edge-aligned with dat
FMD8C16LAx-25Ex Datasheet (2.15 MB)
FMD8C16LAx-25Ex
FIDELIX
2.15 MB
512m(32mx16) low power ddr sdram.
FMD8C16LAx 25Ex 512M(32Mx16) Low Power DDR SDRAM Rev. 0.2, Jul. ‘12 Revision 0.2 Jul. 2012 1 Document Title 512M(32Mx16) Low Power DDR SDR.
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