74ABT377 Datasheet (Fairchild Semiconductor)

74ABT377 Description

The ABT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputsThe common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOWThe register is fully edge-triggeredThe state of each D input, one setup time before the LOW-to

Features

* s Clock enable for address and data synchronization applications s Eight edge-triggered D-type flip-flops s Buffered common clock s See ABT273 for master reset version s See ABT373 for transparent latch version s See ABT374 for 3-STATE version s Output sink capability of 64 mA, source capability of

74ABT377 Datasheet - Fairchild Semiconductor

74ABT377, Octal D-Type Flip-Flop