74ABT377 Datasheet - Fairchild Semiconductor

Octal D-Type Flip-Flop

74ABT377 Features

* s Clock enable for address and data synchronization applications s Eight edge-triggered D-type flip-flops s Buffered common clock s See ABT273 for master reset version s See ABT373 for transparent latch version s See ABT374 for 3-STATE version s Output sink capability of 64 mA, source capability of

74ABT377 General Description

The ABT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to.

74ABT377 Datasheet (101.67 KB)

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74ABT377

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Fairchild Semiconductor

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101.67 KB

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Octal d-type flip-flop.
74ABT377 Octal D-Type Flip-Flop with Clock Enable January 1993 Revised November 1999 74ABT377 Octal D-Type Flip-Flop with Clock Enable General Descr.

📁 Related Datasheet

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74ABT374 Octal D-Type Flip-Flop (Fairchild Semiconductor)

74ABT374A Octal D-type flip-flop (NXP)

74ABT377A Octal D-type flip-flop (NXP)

74ABT32 Quad 2-input OR gate (NXP)

74ABT32 Quad 2-input OR gate (nexperia)

74ABT32D Quad 2-input OR gate (nexperia)

74ABT32PW Quad 2-input OR gate (nexperia)

74ABT00 Quad 2-input NAND gate (NXP)

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74ABT377 Octal D-Type Flip-Flop Fairchild Semiconductor

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74ABT377 Features

74ABT377 General Description

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