DM74LS109A
Fairchild Semiconductor
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Dual positive-edge-triggered j-k flip-flop. This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted
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54LS109 DM54LS109A D.
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August 1986 Revised March 2000
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DM54LS107A DM74LS107A .
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(Fairchild Semiconductor)
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August 1986 Revised March 2000
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DM74LS112A - Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
(Fairchild Semiconductor)
DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
August 1986 Revised March 2000
DM74.
DM74LS112A - NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS
(National Semiconductor)
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DM74LS123 - Dual Retriggerable One-Shot
(Fairchild Semiconductor)
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DM74LS125A - Quad 3-STATE Buffer
(Fairchild Semiconductor)
DM74LS125A Quad 3-STATE Buffer
August 1986 Revised March 2000
DM74LS125A Quad 3-STATE Buffer
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This device contains four independe.