DM74LS139
National Semiconductor
165.29kb
Decoders/demultiplexers. These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications requiring ve
TAGS
📁 Related Datasheet
DM74LS132 - Quad 2-Input NAND Gate
(Fairchild Semiconductor)
DM74LS132 Quad 2-Input NAND Gate with Schmitt Trigger Input
August 1986 Revised March 2000
DM74LS132 Quad 2-Input NAND Gate with Schmitt Trigger Inp.
DM74LS132 - NAND Gates
(National Semiconductor)
DM54LS132 DM74LS132 Quad 2-Input NAND Gates with Schmitt Trigger Inputs
DM54LS132 DM74LS132 Quad 2-Input NAND Gates with Schmitt Trigger Inputs
Gene.
DM74LS136 - Quad 2-Input Exclusive-OR Gate
(Fairchild Semiconductor)
DM74LS136 Quad 2-Input Exclusive-OR Gate with Open-Collector Outputs
October 1988 Revised March 2000
DM74LS136 Quad 2-Input Exclusive-OR Gate with O.
DM74LS138 - Decoder/Demultiplexer
(Fairchild Semiconductor)
DM74LS138 • DM74LS139 Decoder/Demultiplexer
August 1986 Revised March 2000
DM74LS138 • DM74LS139 Decoder/Demultiplexer
General Description
These Sch.
DM74LS138 - Decoders/Demultiplexers
(National Semiconductor)
54LS138 DM54LS138 DM74LS138 54LS139 DM54LS139 DM74LS139 Decoders Demultiplexers
June 1989
54LS138 DM54LS138 DM74LS138 54LS139 DM54LS139 DM74LS139 De.
DM74LS139 - Decoder/Demultiplexer
(Fairchild Semiconductor)
DM74LS138 • DM74LS139 Decoder/Demultiplexer
August 1986 Revised March 2000
DM74LS138 • DM74LS139 Decoder/Demultiplexer
General Description
These Sc.
DM74LS10 - Triple 3-Input NAND Gate
(Fairchild Semiconductor)
DM74LS10 Triple 3-Input NAND Gate
August 1986 Revised March 2000
DM74LS10 Triple 3-Input NAND Gate
General Description
This device contains three in.
DM74LS10 - Triple 3-Input NAND Gates
(National Semiconductor)
54LS10 DM54LS10 DM74LS10 Triple 3-Input NAND Gates
June 1989
54LS10 DM54LS10 DM74LS10 Triple 3-Input NAND Gates
General Description
This device cont.
DM74LS107A - Dual Negative-Edge- Triggered Master-Slave J-K Flip-Flops
(National Semiconductor)
DM54LS107A DM74LS107A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs
June 1989
DM54LS107A DM74LS107A .
DM74LS109A - Dual Positive-Edge-Triggered J-K Flip-Flop
(Fairchild Semiconductor)
DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop with Preset, Clear, and Complementary Outputs
June 1986 Revised March 2000
DM74LS109A Dual Pos.