DM74LS112A Datasheet - Fairchild Semiconductor

DM74LS112A - Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop

This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs.

The J and K data is processed by the flip-flop on the falling edge of the clock pulse.

The clock triggering occurs at a voltage level and is not directly related to the transition time of the fall

Datasheet Details

DM74LS112A

Fairchild Semiconductor

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Dual negative-edge-triggered master-slave j-k flip-flop.

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