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MM74HC139 - Dual 2-To-4 Line Decoder

MM74HC139 Description

MM74HC139 Dual 2-To-4 Line Decoder September 1983 Revised February 1999 MM74HC139 Dual 2-To-4 Line Decoder General .
The MM74HC139 decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications.

MM74HC139 Features

* s Typical propagation delays
* Select to outputs (4 delays): 18 ns Select to output (5 delays): 28 ns Enable to output: 20 ns s Low power: 40 µW quiescent supply power s Fanout of 10 LS-TTL devices s Input current maximum 1 µA, typical 10 pA Ordering Code: Order Number MM74HC139M MM74HC139S

MM74HC139 Applications

* It possesses the high noise immunity and low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low power Schottky TTL logic. The MM74HC139 contain two independent one-of-four decoders each with a single active low enable input (G1, or G2). Data on the select inp

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Dual 2-To-4 Line Decoder Fairchild
Fairchild MM74HC139-like datasheet