Description
GS81302TT06/11/20/38E-500/450/400/350 165-Bump BGA Commercial Temp Industrial Temp 144Mb SigmaDDRTM-II+ Burst of 2 SRAM 500 MHz *350 MHz 1.8.
Table
Symbol
Description
Type Comments
SA
Synchronous Address Inputs
Input.
R/W
Synchronous Read/Write
Input
High: Read Low: Write.
Features
* 2.5 Clock Latency
* Simultaneous Read and Write SigmaDDRTM Interface
* JEDEC-standard pinout and package
* Double Data Rate interface
* Byte Write controls sampled at data-in time
* Burst of 2 Read and Write
* Dual-Range On-Die Termination (O
Applications
* Therefore, the SigmaDDR-II+ SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs are unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed Common I/O SRAM data bandwidth in half. Burst Operations
