GS88118 Datasheet - GSI

GS88118 (GS88118 / GS88136T) Sync Burst SRAMs

Applications The GS88118//36T is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging f.

GS88118 Features

* FT pin for user-configurable flow through or pipelined operation

* Single Cycle Deselect (SCD) Operation

* IEEE 1149.1 JTAG-compatible Boundary Scan

* On-chip write parity checking; even or odd selectable

* 3.3 V +10%/

* 5% core power supply

GS88118_GSI.pdf