HI3512 Datasheet - Hisilicon

HI3512 H.264 Encoding and Decoding Processor

HI3512 Features

* CPU Core

* ARM926EJ-S, 16 KB instruction cache, and 16 KB data cache

* Embedded close coupling memory with 2 KB instruction

* 32-bit RISC processor with the Harvard architecture

* Built-in MMU supporting various open operating systems

* Up to 288 MHz operating frequency Video Interfa

Datasheet Details

HI3512

Hisilicon

273.71 KB

H.264 encoding and decoding processor.

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