HI3512 - H.264 Encoding and Decoding Processor

Product Overview

Hisilicon

Part number	HI3512
Manufacturer	Hisilicon
File Size	273.71 KB
Description	H.264 Encoding and Decoding Processor
Datasheet	HI3512 Datasheet
Additional preview pages of the HI3512 datasheet.

CPU Core.
ARM926EJ-S, 16 KB instruction cache, and 16 KB data cache.
Embedded close coupling memory with 2 KB instruction.
32-bit RISC processor with the Harvard architecture.
Built-in MMU supporting various open operating systems.
Up to 288 MHz operating frequency Video Interfaces.
Input.
2 channels of BT.656/601 YCrCb 4:2:2, 8 bits. Each interface supports two channels of BT.656 multiplex video input. SMPTE296M 720P, YC 4:2:2, 16 bits CCD and CMOS digital inter.

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Published: Feb 17, 2014 |