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74LS112 Datasheet - Hitachi Semiconductor

74LS112 Dual J-K Negative-edge-triggered Flip-Flops

19.20 20.00 Max 16 9 7.40 Max 6.30 Unit: mm 1 1.3 1.11 Max 8 0.51 Min 2.54 Min 5.06 Max 7.62 2.54 ± 0.25 0.48 ± 0.10 0.25 0.05 0° 15° Hitachi Code JEDEC EIAJ Weight (reference value) + 0.13 DP-16 Conforms Conforms 1.07 g Unit: mm 10.06 10.5 Max 16 9 5.5 1 0.22 ± 0.05 0.20 ± 0.04 8 0.80 Max 2.20 Max 0.20 7.80 + 0.30 1.15 0° 8° 0.70 ± 0.20 1.27 0.42 ± 0.08 0.40 ± 0.06 0.12 M Hitachi Code JEDEC EIAJ Weight (reference value) FP-16D.

74LS112 Datasheet (76.76 KB)

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Datasheet Details

Part number:

74LS112

Manufacturer:

Hitachi Semiconductor

File Size:

76.76 KB

Description:

Dual j-k negative-edge-triggered flip-flops.

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TAGS

74LS112 Dual J-K Negative-edge-triggered Flip-Flops Hitachi Semiconductor

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