HD74HC4040 Datasheet PDF - Hitachi Semiconductor 12-stage Binary Counter Specs

HD74HC4040 - 12-stage Binary Counter

Datasheet Summary

Description

The HD74HC4040 is a 12-stage counter.

This device is incremented on the falling edge (negative transition) of the input clock, and all its output is reset to a low level by applying a logical high on its reset input.

Features

High Speed Operation: tpd (Clock to Q1) = 15 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table C Reset L L X X: Irrelevant H Outputs State No change Advance to next stage All outputs are low HD74HC4040 Pin Arrangement Q12 Q6 Q5 Q7 Q4 Q3 Q2 GND 1 2 3 4 5 6 7 8 (Top view) Q6 Q5 Q7 Q4.

Datasheet Details

Part number	HD74HC4040
Manufacturer	Hitachi Semiconductor
File Size	54.09 KB
Description	12-stage Binary Counter
Datasheet	HD74HC4040 Datasheet
Additional preview pages of the HD74HC4040 datasheet.

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Full PDF Text Transcription

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HD74HC4040 12-stage Binary Counter Description The HD74HC4040 is a 12-stage counter. This device is incremented on the falling edge (negative transition) of the input clock, and all its output is reset to a low level by applying a logical high on its reset input.

Published: Mar 23, 2005 |