* Standard SDRAM Protocol Internal 4bank operation Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V All device pins are compatible with LVTTL interface Low Voltage interface to reduce I/O power 8,192 Refresh cycles / 64ms Programmable CAS latency of 2 or 3 Programmable Burst Length and Burst Type
H57V2582GTR-60J Datasheet (227.17 KB)
H57V2582GTR-60J
Hynix Semiconductor
227.17 KB
256mb synchronous dram based on 8m x 4bank x8 i/o.
256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O
256M (32Mx8bit) Hynix SDRAM Memory
Memory Cell Array
- Organized as 4banks of 8,388,608 x 8
This .
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