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H57V2582GTR-60J - 256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O

This page provides the datasheet information for the H57V2582GTR-60J, a member of the H57V2582GTR-60I 256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O family.

Datasheet Summary

Description

and is subject to change without notice.

Hynix does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • Standard SDRAM Protocol Internal 4bank operation Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V All device pins are compatible with LVTTL interface Low Voltage interface to reduce I/O power 8,192 Refresh cycles / 64ms Programmable CAS latency of 2 or 3 Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst.
  • -40oC ~ 85oC Operation Package Type : 54_Pin TSOPII This pr.

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Datasheet Details

Part number H57V2582GTR-60J
Manufacturer Hynix Semiconductor
File Size 227.17 KB
Description 256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O
Datasheet download datasheet H57V2582GTR-60J Datasheet
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Full PDF Text Transcription

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256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O 256M (32Mx8bit) Hynix SDRAM Memory Memory Cell Array - Organized as 4banks of 8,388,608 x 8 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Aug. 2009 1 111 Synchronous DRAM Memory 256Mbit H57V2582GTR-xxI Series Document Title 256Mbit (32M x8) Synchronous DRAM Revision History Revision No. 0.1 1.0 History Preliminary Release Draft Date Jun. 2009 Aug. 2009 Remark Rev 1.0 / Aug.
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