H57V2582GTR-60J, H57V2582GTR-60I Datasheet (Hynix Semiconductor) - 256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O

H57V2582GTR-60J, H57V2582GTR-60I, 256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O

and is subject to change without notice.

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Rev 1.0 / Aug.

2009 1 111 Synchronous DRAM Memory 256Mbit H57V2582GTR-xxI Series Document Title 256Mbit (32M x8) Synchronous DRAM Revision History Revis

H57V2582GTR-60J Features

* Standard SDRAM Protocol Internal 4bank operation Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V All device pins are compatible with LVTTL interface Low Voltage interface to reduce I/O power 8,192 Refresh cycles / 64ms Programmable CAS latency of 2 or 3 Programmable Burst Length and Burst Type