H5DU1262GTR Datasheet (Hynix Semiconductor)

H5DU1262GTR, 128Mb DDR SDRAM

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Rev.

1.0 / May 2009 1 www.DataSheet4U.com H5DU1262GTR Series Revision History Revision No.

0.1 1.0 First version Release History Draft Date

H5DU1262GTR Features

* VDD, VDDQ = 2.3V min ~ 2.7V max (Typical 2.5V Operation +/- 0.2V for DDR266, 333 ,400 and 500) All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirec