Description
16Mb Synchronous DRAM based on 512K x 2Bank x16 I/O Document Title 2Bank x 512K x 16bits Synchronous DRAM Revision History Revision No.0.1 1.0 Histo.
and is subject to change without notice.
Features
* Voltage: VDD, VDDQ 3.3V supply voltage All device pins are compatible with LVTTL interface JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin pitch (Lead or Lead Free Package) All inputs and outputs referenced to positive edge of system
Applications
* which require large memory density and high bandwidth. HY57V161610F-Series is organized as 2banks of 524,288x16. HY57V161610F-Series is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data