* Standard SDRAM Protocol
* Internal 4bank operation
* Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V
* All device pins are compatible with LVTTL interface
* Low Voltage interface to reduce I/O power
* 8,192 Refresh cycles / 64ms
* Programmable CAS latency of 2 or 3
HY57V561620FLT-5 Datasheet (727.86 KB)
HY57V561620FLT-5
Hynix Semiconductor
727.86 KB
256m (16m x 16bit) hynix sdram memory.
256Mb Synchronous DRAM based on 4M x 4Bank x16 I/O 256M (16Mx16bit) Hynix SDRAM Memory Memory Cell Array - Organized as 4banks of 4,194,304 x 16 This.
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