HY57V561620FT-H - 256M (16M x 16bit) Hynix SDRAM Memory
and is subject to change without notice.
Hynix does not assume any responsibility for use of circuits described.
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Rev 1.2 / Dec.
2009 1 111 Synchronous DRAM Memory 256Mbit HY57V561620F(L)T(P) Series Document Title 256Mbit (16M x16) Synchronous DRAM Revision Histo
HY57V561620FT-H Features
* Standard SDRAM Protocol
* Internal 4bank operation
* Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V
* All device pins are compatible with LVTTL interface
* Low Voltage interface to reduce I/O power
* 8,192 Refresh cycles / 64ms
* Programmable CAS latency of 2 or 3
