HY5S5B2CLFP-6E 256M (8Mx32bit) Mobile SDRAM

Hynix Semiconductor

Description

256MBit MOBILE SDR SDRAMs based on 2M x 4Bank x32 I/O Specification of 256M (8Mx32bit) Mobile SDRAM Memory Cell Array - Organized as 4banks of 2,097.
and is subject to change without notice.

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Datasheet Specifications

Part number: HY5S5B2CLFP-6E
Manufacturer: Hynix Semiconductor
File Size: 1.09 MB
Datasheet: HY5S5B2CLFP-6E_HynixSemiconductor.pdf
Description: 256M (8Mx32bit) Mobile SDRAM

Features

* Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK)
* MULTIBANK OPERATION - Internal 4bank operation - During burst Read or Write operation, burst Read or Write for a different bank is performed. - Duri

Applications

* which requires large memory density and high bandwidth. It is organized as 4banks of 2,097,152 x32. Mobile SDRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Mobile SDRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output dat

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HY5S5B2CLFP-6E 256M 8Mx32bit Mobile SDRAM Hynix Semiconductor

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