HMP31GP7AFR4C-Y5 Datasheet - Hynix

HMP31GP7AFR4C-Y5 240pin Registered DDR2 SDRAM DIMMs based on 2Gb

and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1 / Jan. 2009 1 1240pin Registered DDR2 SDRAM DIMMs SPEED GRADE & KEY PARAMETERS Y5 (DDR2-667) Speed@CL3 Speed@CL4 Speed@CL5 Speed@CL.

HMP31GP7AFR4C-Y5 Features

* JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface 8 Bank architecture Posted CAS Programmable CAS Latency 3, 4, 5, 6 OCD (Off-Chip Driver Impedance Adjustment) ODT (On-Die Termination

HMP31GP7AFR4C-Y5 Datasheet (190.03 KB)