* JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface Posted CAS Programmable CAS Latency 3, 4, 5, 6 OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) Fully differ
HYMP512S64CLP8-E3 Datasheet (295.06 KB)
HYMP512S64CLP8-E3
Hynix
295.06 KB
200pin unbuffered ddr2 sdram so-dimms based on 512 mb.
200pin Unbuffered DDR2 SDRAM SO-DIMMs based on 512 Mb C ver.
This Hynix unbuffered Small Outline Dual In-Line Memory Module(DIMM) series consists of 5.
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