8P391208 Datasheet (IDT) - Low Additive Jitter 2:8 Buffer

8P391208, Low Additive Jitter 2:8 Buffer

8P391208 is intended to take 1 or 2 reference clocks, select between them, using a pin selection and generate up to 8 outputs that are the same as the reference frequency.

8P391208 supports two output banks, each with its own power supply.

All outputs in one bank would generate the same output frequ

8P391208 Features

* Two differential inputs support LVPECL, LVDS, HCSL or LVCMOS reference clocks

* Accepts input frequencies ranging from 1PPS (1Hz) to 700MHz (up to 1GHz when configured into HCSL output mode at 3.3V)

* Select which of the two input clocks is to be used as the reference clock