8P34S1102 - 1:2 LVDS 1.8V / 2.5V Fanout Buffer

Renesas

Datasheet Details

The 8P34S1102 is a high-performance differential LVDS fanout buffer.

Two low skew, low additive jitter LVDS output pairs.
One differential clock input pair.
Differential CLK, nCLK pairs can accept the following differential input levels: LVDS, CML.
Maximum input clock frequency: 51.2GHz.
Output skew: 3ps (typical).
Propagation delay: 400ps (maximum).
Low additive phase jitter, RMS; fREF = 156.25MHz, 10kHz.
20MHz: 34fs (typical).
Device current consumption (IDD):.
40mA typical: 1.8V.
50mA typical: 2.

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Published: Sep 25, 2023 |