9DB1233 Datasheet - IDT

9DB1233 Twelve Output Differential Buffer

The 9DB1233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB1233 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selecta.

9DB1233 Features

* 12 - 0.7V current mode differential HCSL output pairs Features/Benefits

* 3 Selectable SMBus Addresses/Mulitple devices can share the same SMBus Segment

* 12 OE# pins/Hardware control of each output

* PLL or bypass mode/PLL can dejitter incoming clock

* Sel

9DB1233-IDT.pdf