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9DB633 Datasheet - Renesas

9DB633 Differential Buffer

The 9DB633 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB633 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectab.

9DB633 Features

* Benefits:

* OE# pins/Suitable for Express Card applications

* PLL or bypass mode/PLL can dejitter incoming clock

* Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's

* Spread Spectrum Compatible/tracks spreading input clock for low EMI

* SMB

9DB633 Datasheet (297.84 KB)