Description
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The IDT54/74AHCT573 are 8-bit latches built using advanced CEMOS'.
, a dual metal CMOS technology.
Features
* Equivalent to ALS speeds and output drive over full temperature and voltage supply extremes
* 1Ons typical data to output delay
* IOL = 14mA over full military temperature range
* CMOS power levels (5/lW typo static)
* Both CMOS and TTL output compatible
Applications
* The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. PIN CONFIGURATIONS
OE
Do 0,
O2
