IDT71V65702 Datasheet - IDT

IDT71V65702 (IDT71V65702 / IDT71V65902) Synchronous ZBT SRAMs

The IDT71V65702/5902 are 3.3V high-speed 9,437,184-bit (9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x 18. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus they have been given the name ZBTTM, or Zero Bus Tur.

IDT71V65702 Features

* 256K x 36, 512K x 18 memory configurations Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized output buffer enable eliminates the need to control OE Single R/W (READ/WRITE) control pin 4

IDT71V65702 Datasheet (520.57 KB)