IS43DR81280C - DDR2 DRAM

ISSI

IS43DR81280C Datasheet Preview — Preview of IS43DR81280C PDF

Datasheet Details

Part number	IS43DR81280C
Manufacturer	ISSI
File Size	872.14 KB
Description	DDR2 DRAM
Datasheet	IS43DR81280C-ISSI.pdf

IS43DR81280C Product details

Description

MAY 2013 ISSI's 1Gb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation.The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls.ADDRESS TABLE Parameter Configuration Refresh Count 128M x 8 16M x 8 x 8 banks 8K/64ms 64M x 16 8M x 16 x 8 banks 8K/64ms Row Addressing 16K (A0-A13) 8K (A0-A12) Column Addressing 1K (A0-A9) Bank Addressing BA0 - BA2 1K

Features

Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V.
JEDEC standard 1.8V I/O (SSTL_18-compatible).
Double data rate interface: two data transfers per clock cycle.
Differential data strobe (DQS, DQS).
4-bit prefetch architecture.
On chip DLL to align DQ and DQS transitions with CK.
8 internal banks for concurrent operation.
Programmable CAS latency (CL) 3, 4, 5, 6 and 7 supported.
Posted CAS and programmable additive laten.

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Published: Aug 1, 2016 |