IS43LR16200C Datasheet - ISSI

IS43LR16200C 1M x 16Bits x 2Banks Mobile DDR SDRAM

The IS43LR16200C is 33,554,432 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 2 banks of 1,048,576 words x 16 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2N prefetch architecture with an .

IS43LR16200C Features

* JEDEC standard 1.8V power supply

* Two internal banks for concurrent operation

* MRS cycle with address key programs - CAS latency 2, 3 (clock) - Burst length (2, 4, 8, 16) - Burst type (sequential & interleave)

* Fully differential clock inputs (CK, /CK)

IS43LR16200C-ISSI.pdf