* Internal self-timed write cycle
* Individual Byte Write Control and Global Write
* Clock controlled, registered address, data and control
* Burst sequence control using MODE input
* Three chip enable option for simple depth expansion and address pipelining
* Common data inp
IS61LPS25618EC Datasheet (2.16 MB)
IS61LPS25618EC
ISSI
2.16 MB
Single cycle deselect sram.
IS61(4)LPS12836EC/IS61(4)VPS12836EC/IS61(4)LPS12832EC IS61(4)VPS12832EC/IS61(4)LPS25618EC/IS61(4)VPS25618EC 128K x36/32 and 256K x18 4Mb, ECC, SYNCHRO.
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