* Internal self-timed write cycle
* Individual Byte Write Control and Global Write
* Clock controlled, registered address, data and control
* Burst sequence control using MODE input
* Three chip enable option for simple depth ex- pansion and address pipelini
IS61LPS25618A Datasheet (540.52 KB)
IS61LPS25618A
Integrated Silicon Solution
540.52 KB
4mb synchronous pipelined single cycle deselect static ram.
IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A
128K x 32, 128K x 36, 256K x 18
DECEMBER 2013
4 Mb SYNCHR.
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