Description
IS61QDPB44M18A/A1/A2 IS61QDPB42M36A/A1/A2 4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.5 Cycle Read Latency) NOVEMBER 2014 .
at page 6 for each ODT option.
Features
* 2Mx36 and 4Mx18 configuration available.
* On-chip Delay Locked Loop (DLL) for wide data valid window.
* Separate independent read and write ports with concurrent read and write operations.
* Synchronous pipeline read with late write operation.
* Double Data Rate (DDR) interfac
Applications
* where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance
