SEMD13 - NPN/PNP Silicon Digital Transistor Array Preliminary data
SEMD13 NPN/PNP Silicon Digital Transistor Array Preliminary data Switching circuit, inverter, interface circuit, driver circuit Two (galvanic) internal isolated NPN/PNP Transistors in one package Built in bias resistor (R1=4.7kΩ, R2 =47kΩ) Tape loading orientation Top View 3 2 1 4 5 3 6 1 2 Marking on SOT666 package (for example W R) corresponds to pin 1 of device Position in tape: pin 1 same of feed hole side C1 6 B2 5 E2 4 R2 R1 TR1 R2 1 2 B1 3 C2 EHA07176
