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HYS64D16301HU-5-C 184-Pin Unbuffered Dual-In-Line Memory Modules

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Description

D a t a S he et , V 1.0, J u l y 2 00 3 HYS[64/72]D64x20HU-[5/6]-C HYS[64/72]D32x00HU-[5/6]-C H Y S 64 D 1 6 x 0 1 H U - [ 5 / 6 ] - C 1 8 4 - P i n.
and charts stated herein.

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Applications

* One rank 16M x 64, 32M × 64, 32M × 72 and two ranks 64M × 64, 64M × 72 organization JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5V (±0.2V) power supply Built with 256 Mbit DDR SDRAM in P-TSOPII-66-1 package Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequen

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184-Pin Unbuffered Dual-In-Line Memory Modules Infineon
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