Description
D a t a S he et , V 1.1, J u l y 2 00 3 HYS[64/72]D64x20GU-x-B HYS[64/72]D32x00[G/E]U-x-B HYS64D16301GU-x-B 1 8 4 - P i n U n b u f f er e d D u a l.
and charts stated herein.
Applications
* One rank 16M x 64, 32M × 64, 32M × 72 and two ranks 64M × 64, 64M × 72 organization JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5V (±0.2V) power supply Built with 256 Mbit DDR SDRAM in P-TSOPII-66-1 package Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequen
