M2020-2021 Datasheet - Integrated Circuit Systems

M2020-2021 VCSO BASED CLOCK PLL

The M2020/21 is a VCSO (Voltage Controlled SAW Oscillator) based clock jitter attenuator PLL designed for clock jitter attenuation and frequency translation. The device is ideal for generating the transmit reference clock for optical network systems supporting 2.5-10 GB data rates. It can serve to j.

M2020-2021 Features

* Integrated SAW (surface acoustic wave) delay line; low phase jitter of < 0.5ps rms, typical (12kHz to 20MHz or 50kHz to 80MHz)

* Output frequencies of 15 to 700 MHz

* LVPECL clock output (CML and LVDS options available)

* Reference clock inputs support differential LVDS, LVPE

M2020-2021_IntegratedCircuitSystems.pdf