IDT74FCT32932-100 - 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER
The FCT3932 uses phase-lock loop technology to lock the frequency and phase of the feedback to the input reference clock.
It provides a large number of low skew outputs that are configurable in 16 different modes using the CNTRL 1-4 inputs.
A dedicated output, Q_FB, is provided to supply the PLL fe
IDT74FCT32932-100 Features
* 0.5 MICRON CMOS Technology Guaranteed low skew 16 programmable frequency configurations 17 3-state outputs: ±24 mA FCT3932 ±8 mA FCT32932 Output configuration: BANK1: 4 outputs BANK2: 8 outputs BANK3: 5 outputs Dedicated feedback output (Q_FB) Maxim
