79RC32K438 Datasheet - Integrated Device Technology

79RC32K438 Communications Processor

for EJTAG/JTAG pins in Table 1. Changed DDRDM[7:0] from input/output to output only in Tables 1 and 2 and Logic Diagram. Added new section, Voltage Sense Signal Timing, as part of EJTAG description. March 4, 2003: In Table 2, removed “pull-up” from PCI pin category and from GPIO [24] and GPIO[30-26].

79RC32K438 Features

* 32-bit CPU Core

* MIPS32 instruction set

* Cache Sizes: 16KB instruction and data caches, 4-Way set associative, cache line locking, non-blocking prefetches

* 16 dual-entry JTLB with variable page sizes

* 3-entry instruction TLB www.DataSheet4U.com

* 3-entry d

79RC32K438_IntegratedDeviceTechnology.pdf