* Operates at 3.3V VDD/AVDD and 2.5V/3.3V VDDQ
* 1:10 fanout
* 3-level inputs for output control
* External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal
* No external RC network required for PLL loop stability
* Con
IDT5V2528 Datasheet (58.65 KB)
IDT5V2528
Integrated Device
58.65 KB
2.5v / 3.3v phase-lock loop clock driver zero delay buffer.
IDT5V2528/A 2.5 / 3.3V PHASE-LOCK LOOP CLOCK DRIVER 2.5V / 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER INDUSTRIALTEMPERATURERANGE IDT5V2528/A.
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