IDT5V2528 Datasheet - Integrated Device

IDT5V2528 2.5V / 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER

The IDT5V2528 is a high performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. FUNCTIONAL BLOCK DIAGRAM The IDT5V2528 inputs, PLL core, Y0, Y1, and FBOUT buff.

IDT5V2528 Features

* Operates at 3.3V VDD/AVDD and 2.5V/3.3V VDDQ

* 1:10 fanout

* 3-level inputs for output control

* External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal

* No external RC network required for PLL loop stability

* Con

IDT5V2528_IntegratedDeviceTechnology.pdf