IS61DDB22M18 Datasheet (Integrated Silicon Solution) - DDR-II (Burst of 2) CIO Synchronous SRAMs

IS61DDB22M18, DDR-II (Burst of 2) CIO Synchronous SRAMs

The 36Mb IS61DDB21M36 and IS61DDB22M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have a common I/O bus.

The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.

Refer to the Timing Reference Diagra

IS61DDB22M18 Features

* 1M x 36 or 2M x 18.

* On-chip delay-locked loop (DLL) for wide data valid window.

* Common data input/output bus.

* Synchronous pipeline read with self-timed late write operation.

* Double data rate (DDR-II) interface for read and write input ports.