IS61DDB22M18A Datasheet (Integrated Silicon Solution) - 36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM

IS61DDB22M18A, 36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM

The 36Mb IS61DDB21M36A and IS61DDB22M18A are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have a common I/O bus.

The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.

Refer to the Timing Reference Diag

IS61DDB22M18A Features

* 1Mx36 and 2Mx18 configuration available.

* On-chip delay-locked loop (DLL) for wide data valid window.

* Common I/O read and write ports.

* Synchronous pipeline read with self-timed late write operation.

* Double Data Rate (DDR) interface for read and write input ports.

* F