IS61DDP2B44M18A Datasheet, Sram, Integrated Silicon Solution

✔ IS61DDP2B44M18A Features

DESCRIPTION
2Mx36 and 4Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Common I/O read and write ports.
Synchronous pi

✔ IS61DDP2B44M18A Application

where the failure or malfunction of the product can reasonably be expected to cause failure of the life supp

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IS61DDP2B44M18A

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Integrated Silicon Solution

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📄 Datasheet

Description:

72mb ddr-iip cio synchronous sram. * 2Mx36 and 4Mx18 configuration available. * On-chip Delay-Locked Loop (DLL) for wide data valid window. * Common I/O read and write

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SRAM Chip Sync Single 1.8V 72M-Bit 4M x 18 0.45ns 165-Pin LFBGA - Bulk (Alt: IS61DDP2B44M18A-400M3L)

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IS61DDP2B44M18A-400M3L

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IS61DDP2B44M18A 72Mb DDR-IIP CIO SYNCHRONOUS SRAM Integrated Silicon Solution