IS61DDP2B451236A Datasheet, Sram, Integrated Silicon Solution

✔ IS61DDP2B451236A Features

DESCRIPTION
512Kx36 and 1Mx18 configuration available.
On-chip Delay-Locked Loop (DLL) for wide data valid window.
Common I/O read and write ports.
Synchronous

✔ IS61DDP2B451236A Application

where the failure or malfunction of the product can reasonably be expected to cause failure of the life supp

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IS61DDP2B451236A

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Integrated Silicon Solution

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📄 Datasheet

Description:

18mb ddr-iip(burst 4) cio synchronous sram. * 512Kx36 and 1Mx18 configuration available. * On-chip Delay-Locked Loop (DLL) for wide data valid window. * Common I/O read and wri

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Integrated Silicon Solution Inc

SRAM Chip Sync Single 1.8V 18M-Bit 512K x 36 0.45ns 165-Pin LFBGA - Bulk (Alt: IS61DDP2B451236A-400M3L)

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IS61DDP2B451236A-400M3L

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IS61DDP2B451236A 18Mb DDR-IIPBurst CIO SYNCHRONOUS SRAM Integrated Silicon Solution