IS61DDPB22M36 - DDR-IIP (Burst of 2) CIO Synchronous SRAMs
The 72Mb IS61DDPB22M36 and IS61DDPB24M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices.
These SRAMs have a common I/O bus.
The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.
Refer to the Timing Reference Diag
IS61DDPB22M36 Features
* 2M x 36 or 4M x 18.
* On-chip delay-locked loop (DLL) for wide data valid window.
* Common data input/output bus.
* Synchronous pipeline read with self-timed late write operation.
* Double data rate (DDR-IIP) interface for read and write input ports.
