IS61DDPB22M36, IS61DDPB24M18 Datasheet - Integrated Silicon Solution

IS61DDPB22M36 DDR-IIP (Burst of 2) CIO Synchronous SRAMs

The 72Mb IS61DDPB22M36 and IS61DDPB24M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diag.

IS61DDPB22M36 Features

* 2M x 36 or 4M x 18.

* On-chip delay-locked loop (DLL) for wide data valid window.

* Common data input/output bus.

* Synchronous pipeline read with self-timed late write operation.

* Double data rate (DDR-IIP) interface for read and write input ports.

IS61DDPB24M18-IntegratedSiliconSolution.pdf

IS61DDPB22M36 Datasheet Preview — This datasheet PDF includes multiple part numbers: IS61DDPB22M36, IS61DDPB24M18. Please refer to the document for exact specifications by model.

Datasheet Details

Part number:

IS61DDPB22M36, IS61DDPB24M18

Manufacturer:

Integrated Silicon Solution

File Size:

572.22 KB

Description:

Ddr-iip (burst of 2) cio synchronous srams.

Note:

This datasheet PDF includes multiple part numbers: IS61DDPB22M36, IS61DDPB24M18.
Please refer to the document for exact specifications by model.

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