* DESCRIPTION
* 512Kx36 and 1Mx18 configuration available.
* On-chip Delay-Locked Loop (DLL) for wide data valid window.
* Common I/O read and write ports.
* Synchronous pipeline read with self-timed late write operation.
* Double Data Rate (DDR) interface for read and write inpu
IS61DDPB251236A1 Datasheet (509.49 KB)
IS61DDPB251236A1
Integrated Silicon Solution
509.49 KB
18mb ddr-iip(burst 2) cio synchronous sram.
IS61DDPB21M18A/A1/A2 IS61DDPB251236A/A1/A2
1Mx18, 512Kx36 18Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
(2.5 Cycle Read Latency)
ADVANCED INFORMATION JU.
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