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IDT72V255LA CMOS FIFO memories

IDT72V255LA Description

3.3 VOLT CMOS SuperSync FIFO™ 8,192 x 18 16,384 x 18 .
The IDT72V255LA/72V265LA are functionally compatible versions of the IDT72255/72265 designed to run off a 3.

IDT72V255LA Features

* IDT72V255LA IDT72V265LA
* Choose among the following memory organizations: IDT72V255LA 8,192 x 18

IDT72V255LA Applications

* that need to buffer large amounts of data. The input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data is written into the FIFO on every rising edge of WCLK when WEN is asserted. The output port is controlled by a Read Clock (RCLK) input and Read Enable (REN) inp

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CMOS FIFO memories Integrated Device Tech
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