IDT72V2105 Datasheet - Integrated Device Technology

IDT72V2105, CMOS FIFO memories

3.3 VOLT HIGH DENSITY CMOS SUPERSYNC FIFO™ 131,072 x 18 262,144 x 18 .EATURES: * * * * * * *

Features

* Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin functions as a serial

Applications

* that need to buffer large amounts of data. The input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data is written into the FIFO on every rising edge of WCLK when WEN is asserted. The output port is controlled by a Read Clock (RCLK) input and Read Enable (REN) inp

IDT72V2105_IntegratedDeviceTechnology.pdf