IDT72V285 Datasheet - Integrated Device Technology

IDT72V285 CMOS FIFO memories

The IDT72V275/72V285 are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls. These FIFOs offer numerous improvements over previous SuperSync FIFOs, including the following: * The limitation of the frequency of one clock input with r.

www.DataSheet4U.com 3.3 VOLT CMOS SuperSync FIFO™ 32,768 X 18 65,536 X 18 IDT72V275 IDT72V285 .EATURES: Choose among the following memory organizations: IDT72V275 32,768 x 18 IDT72V285 65,536 x 18 Pin-compatible with the IDT72V255/72V265 SuperSync FIFOs 10ns read/write cycle time (6.5ns access time) Fixed, low first word data latency time Auto power down minimizes standby power consumption Master Reset clears entire FIFO Partial Reset clears data, but retains programmable settings R.

IDT72V285 Features

* OW (OR to HIGH in FWFT mode) temporarily and does not disturb the write pointer, programming method, existing timing mode

IDT72V285 Datasheet (187.65 KB)