IS61DDB42M18 - DDR-II (Burst of 4) CIO Synchronous SRAMs

Integrated Silicon Solution

Datasheet Details

Part number	IS61DDB42M18
Manufacturer	Integrated Silicon Solution
File Size	512.68 KB
Description	DDR-II (Burst of 4) CIO Synchronous SRAMs
Datasheet	IS61DDB42M18-IntegratedSiliconSolution.pdf

The 36Mb IS61DDB41M36 and IS61DDB42M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices.

1M x 36 or 2M x 18.
On-chip delay-locked loop (DLL) for wide data valid window.
Common I/O read and write ports.
Synchronous pipeline read with late write operation.
Double data rate (DDR-II) interface for read and write input ports.
Fixed 4-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K) for address and control registering at rising edges only.
Two input clocks (C an.

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Published: Jul 25, 2016 |